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Design & Reuse 作为全球唯一独立的专业IP搜索引擎,已经走过了20个春秋。450多个来自不同国家和地区的IP供应商,选择D&R作为他们与终端用户沟通的桥梁与信息交换的重要渠道。其7X24小时在线的强劲引擎携15,000个持续更新的IP产品,为世界各地35,000多位专业的注册用户提供无可匹敌的IP产品及供应商资源。
Design & Reuse 在全球范围内连续16年坚持开展基于IP复用技术的专业技术大会,为供应商与用户见面交流开创机遇与平台,为IP复用技术的社区建设及发展坚持不懈地做出自己的努力与积极的贡献。
作为其全球IP-SoC Days的重要部份,本活动于七年前登陆中国。2017年9月14日在上海 Design & Reuse 将继续为中国用户及相关供应商带来IP-SoC Day,这将是海内外IP供应商与中国用户面对面交流的IP技术盛会!
本次大会与中芯国际的技术大会(上海2017年9月13日)紧密配合,为您提供一次独一无二的机会来探讨基于IP复用的芯片开发与设计技术发展与挑战,如何应对速度更快、集成度更高、功耗更低的用户需求;与技术专家一起交流最新的IP技术进展及其企业应用,共同探讨创新双赢的商业模式。
1.作为业内人士的您被邀请参与其中
2.约有近20家来自不同国家和地区的IP供应商正积极准备参加此次盛会,请在注册时告诉我们您感兴趣的供应商和IP产品,您将有机会获得与目标供应商单独会面的机会
3.注册参与便有机会获得精美小礼品及大会手册各一份
4.免费提供会议酒店自助午餐,与业内人士交流
IP SoCDays 上海展会指南
Date: September 14th, 2017
Time:
ConferenceTime: 09:00am – 17:30pm
LunchBuffet: 12:00pm – 13:00pm
Venue:
EvergreenLaurel Hotel (Shanghai) 长荣桂冠酒店(上海)
NO. 1136, ZuChongZhiRoad, Pudong District, Shanghai 201203, China
上海市浦东新区祖冲之路1136号,近金科路
Tel: +86-21-80169988
Web: http://www.evergreen-hotel-shanghai.com/
Map:
Join D&R User Group meeting on September 13th and celebrate D&R 20th Anniversary.
This meeting is a brainstorming meeting to explore how D&R services can better serve the worldwide IP community.
5.30 pm |
D&R website and new Alerts |
6.00 p.m |
What’s new in IPMS™ latest version (D&R Intranet IP Management system) for IP consumers and IP providers |
6.30 pm | Let's celebrate D&R 20th anniversary |
9:00 |
Introductory Session
Chairperson : Gabrièle Saucier (D&R) D&R the catalyst of IP business for 2 decades: which vision? which future?
by Gabriele Saucier
CEO, Design & Reuse
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SMIC Solutions for Your Needs
by Hongying Wu
Director of Design Enablement Center, SMIC
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Changing Dynamic in semiconductor industry
by Samir Patel
CEO, Sankalp Semiconductor
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SoC enablers with proven YouIP and Platforms
by John Zhuang
CTO, Brite Semiconductor Inc.
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11:00 |
Break
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11:30 |
Session 2: IoT the next opportunity
Chairperson: Samir Patel (Sankalp SemiConductor) How to design an IoT SoC and get ARM CPU IP for no upfront license fee
by Phil Burr
Senior Product Marketing Manager, ARM
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IP Solutions for Securing IoT Devices
by Matthew Ma
Synopsys Inc.
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IP blocks for Storage, Networking and IoT
by Amit Saxena
VP of Engineering, Mobiveil Inc.
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Awareness of IoT Security vulnerabilities regarding hardware-involved attack scenarios
by Charles Thooris
Sales & Marketing Director, Secure IC S.A.S.
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13:00 |
Lunch Break
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14:00 |
Session 3a: eFPGA a new vision of programmable blocks
Chairperson: Mark Ma (Jiatao China) |
Session 3b: IP based solutions
Chairperson: Philippe Burr ( Arm) |
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eFPGA Comes of Age
by Itsu Wang
Sr Director, Asia Sales and Marketing, QuickLogic Corp.
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Standalone,
Highly Flexible, Low-Power, and Scalable Neural Network DSP for AR/VR,
Automotive, Mobile, and Surveillance Applications
by Wendy Chen
Program Management Director, Asia-Pac IP Business, Cadence Design Systems Inc.
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Flexible Trusted eFPGA
by Imen Baili
Menta S.A.S.
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Building a Silicon Area Optimized Multi-format Video Encoder IP
by Tomi Jalonen
VP Sales, ALLEGRO DVT
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eFPGAs - Revolutionizing the high performance computing landscape
by Eric Law,
Achronix
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Configuring DDR IP to Enhance Design Speed and Minimize Design Footprint
by Bruce Luo,
GM of Greater China, Uniquify Inc.
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15:00 |
Break |
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15:30 |
Session 4a: Design Methodology
Chairperson: Matthew Ma, (Synopsys Inc.) |
Session 4b: Interface IP
Chairperson: Wendy Chen (Cadence Design Systems Inc.) |
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Improving Battery Powered Device Operation Time Thanks to Power Efficient Sleep Mode
by Ying Zhao
Dolphin Integration
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Guide to Choosing the right PCIe Controller+PHY Combo
by Rex Yu
FAE Manager - Asia, PLDA
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Reaching Working Silicon - Addressing the challenges of in-chip conditions on 28nm & FinFET
by Naseer Khan
VP of sales, Moortec Semiconductor Ltd.
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High Speed SERDES new standards
by Yossi Yehiel
VP Sales & Marketing, Silabtech Pvt Ltd.
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Embedded analytics delivers system-wide visibility for debug, safety, security and more...
by Gajinder Panesar
CTO, UltraSoC Technologies Ltd.
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USB 3.1
by Blend Fang
Senior Sales Director at Corigine, Inc.
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16:30 |
Lucky Draw
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Agenda
Time |
Agenda |
09:15 |
"Welcome " |
09:45 |
"IP Market Demands and Offers" |
10.15 |
Break |
10.45 |
"Evolution of Analog to Digital Converters" |
11.15 |
"Fractional-N PLLs : Versatile Frequency Synthesis Building Block" |
11.45 |
"New struggle on multimedia Audio Converters: How Dolphin Integration reduced the fabrication costs?" |
12.15 |
Lunch |
13.30 |
"8-bit to 32-bit processor and micro controller IP from CAST" |
14.00 |
"Why using Single Root I/O Virtualization (SR-IOV) can help improve your design performance and reduce costs" |
14.30 |
"Data Management Engine " |
15.30 |
Break |
16. 30 |
"Seminar on Enterprise Management Platform: From IP to License management" |
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